发明名称 Semiconductor device or printed wiring board design method and design support system that implements settings by using a semiconductor device model that expresses parasitic elements that occur when packaged
摘要 Correction circuit models are acquired for correcting electrical characteristic parameters that change upon mounting on a board. The correction circuit models are added to a separate model that represents a separate semiconductor device in isolation to create a semiconductor device model that represents the semiconductor device in a board-mounted state. An equivalent circuit model that represents an adjustment-object system is connected to the semiconductor device model that was created, and based on the semiconductor device model to which the equivalent circuit model is connected, adjustment-object values relating to the adjustment-object system are calculated. These adjustment-object values are compared with limit values that were determined in advance, and based on the results of comparison, a design guide is determined for adjusting the adjustment-object system.
申请公布号 US2009327981(A1) 申请公布日期 2009.12.31
申请号 US20090457930 申请日期 2009.06.25
申请人 ELPIDA MEMORY, INC. 发明人 NAKAMURA SATOSHI;HARA TSUTOMU;KATAGIRI MITSUAKI;HIROSE YUKITOSHI;ITAYA SATOSHI;IWAKURA KEN
分类号 G06F17/50 主分类号 G06F17/50
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