| 摘要 |
In general, in one aspect, the disclosure describes a prefix tree adder. The adder may be used to add two strings of bits or multiply a string of bits by 3. First group carry generate and propagate signals are calculated directly from inputs to the adder using Ling equations and static logic. The previously calculated group carry generate and propagate signals are propagated through the adder to calculate additional group carry generate and propagate signals. A conditional summer receives a plurality of inputs for the bits and calculates multiple sums for the bits. The conditional summer selects an appropriate sum for the bits based on carry signals utilized as control signals. The number of delay stages required to calculate the sum is LOGXN+1, wherein N is number of bits in the adder and X is number of bits in a group.
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