发明名称 EDGE-TIMING ADJUSTMENT CIRCUIT
摘要 According to some embodiments, a method and system are provided to receive a clock input at a first clock adjustment tuner, receive the clock input at a second clock adjustment tuner, output a tuned inverted rising clock signal via the first clock adjustment tuner, output a tuned inverted falling clock signal via the second clock adjustment tuner, receive the inverted rising clock signal and the inverted falling clock signal at a clock synchronizer, output a synchronized tuned clock signal via the clock synchronizer, receive the synchronized tuned clock signal at a third clock adjustment tuner, and output a tuned clock signal. The first clock adjustment tuner and the second clock adjustment tuner provide coarser adjustments than the third clock adjustment tuner.
申请公布号 US2009322393(A1) 申请公布日期 2009.12.31
申请号 US20080146663 申请日期 2008.06.26
申请人 NEIDENGARD MARK L 发明人 NEIDENGARD MARK L.
分类号 H03K5/12 主分类号 H03K5/12
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