发明名称 Integrated Circuit Routing and Compaction
摘要 An iterative technique is used to automatically route nets and alter spacing of an integrated circuit design to achieve a fully routed and compact result. After identifying cells rows and channel, which are gaps between the rows, the technique determines which nets should be routed in which areas. Spine routing is used for nets than span more than one row or channel. Alter the space between rows, larger or smaller, which will allow routing of the nets.
申请公布号 US2009327990(A1) 申请公布日期 2009.12.31
申请号 US20090552183 申请日期 2009.09.01
申请人 PULSIC LIMITED 发明人 WALLER MARK
分类号 G06F17/50 主分类号 G06F17/50
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