发明名称 |
DECODE PROCESSING DEVICE, PROCESSOR, ELECTRONIC DEVICE, DECODE PROCESSING METHOD, AND DECODE PROCESSING PROGRAM |
摘要 |
<p>Provided is a decode processing device capable of reduing the number of cycles required to decode a variable length code as represented by encoding TC or T1s of CAVLC. The decode processing device decodes a variable length code bit stream including a prefix and a suffix following the prefix. The decode processing device includes: a bit-storage control means for holding part of the variable length code bit stream and enabling this holding process operation to be controlled; and a control information and decode address generation control means for generating, based on the prefix of the variable length code bit stream, a decode address used to refer to a decode table, which is necessary for decoding, and generating control information used to update the variable length code bit stream for the bit-storage control means. A process for outputting the decode address is performed simultaneously with a process for updating the variable length code bit stream.</p> |
申请公布号 |
WO2009157250(A1) |
申请公布日期 |
2009.12.30 |
申请号 |
WO2009JP57832 |
申请日期 |
2009.04.20 |
申请人 |
NEC CORPORATION;ISHIHARA, NOZOMI |
发明人 |
ISHIHARA, NOZOMI |
分类号 |
H03M7/40;G06T9/00;H04N1/41 |
主分类号 |
H03M7/40 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|