发明名称 Method of fabricating a via attached to a bond pad utilizing a tapered interconnect
摘要 Various embodiments include a method of forming an interconnect comprising forming at least two vias in a substrate, forming a conductive pad on a surface of the substrate, forming at least one tapered conductive segment on the surface of the substrate coupled to the conductive pad, wherein only a first via of the at least two vias is formed substantially beneath the conductive pad and is coupled to the conductive pad, a second via of the at least two vias is coupled to the conductive pad by a first one of the at least one tapered conductive segments, the first one of the tapered conductive segments having a first end having a first width and a second end having a second width, the first end being connected to the second via and the second end being connected to the conductive pad, the first width being less than the second width.
申请公布号 US7638419(B2) 申请公布日期 2009.12.29
申请号 US20070948748 申请日期 2007.11.30
申请人 INTEL CORPORATION 发明人 JENSEN ERIK W.
分类号 H01L21/44;H01L23/00;H01L23/48;H05K1/02;H05K1/11;H05K1/18;H05K3/00;H05K3/34;H05K3/42;H05K7/10 主分类号 H01L21/44
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