| 摘要 |
The embodiments of the present invention provide methods for choosing a via layout pattern(s) for power distribution network in a package for a semiconductor die. The chosen via layout pattern allows the power distribution network to meet the limitation on the loop inductance in order to avoid causing a large DeltaV affecting the functionality of semiconductor devices on the die. In addition, the chosen via layout pattern also meets the limitation of total number of vias allowed for the power distribution network in the package.
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