发明名称 Data transfer apparatus by direct memory access controller
摘要 A DMA apparatus which reads data corresponding to a descriptor from memory, and a dividing unit in a descriptor management device divides one descriptor into a plurality of sub-descriptors. A plurality of DMA controllers produce a plurality of reading requests for reading data corresponding to the plurality of sub-descriptors from the memory. A memory controller reads the corresponding data from the memory according to the plurality of reading requests.
申请公布号 US7640374(B2) 申请公布日期 2009.12.29
申请号 US20050196469 申请日期 2005.08.04
申请人 FUJITSU LIMITED 发明人 TOMOZAKI TOSHIHIRO;YOSHIDA TOSHIYUKI;OGAWA YUICHI;HANEDA TERUMASA;HANAOKA YUUJI
分类号 G06F3/00;G06F12/00 主分类号 G06F3/00
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