| 发明名称 |
STRESS LINER FOR STRESS ENGINEERING |
| 摘要 |
<p>A stress liner having first and second stress type is provided over a first type and a second type transistor to improve reliability and performance without incurring area penalties or layout deficiencies.</p> |
| 申请公布号 |
SG157344(A1) |
申请公布日期 |
2009.12.29 |
| 申请号 |
SG20090036823 |
申请日期 |
2009.06.01 |
| 申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING LTD |
发明人 |
GON LEE JAE;JINGZE TIAN;SENG TAN SHYUE;LUONA GOH;WEI LU;QUEK ELGIN |
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