发明名称 Method of transforming serial scrambler to parallel scrambler, parallel scrambler and double-edge-triggered register with XOR operation
摘要 A method of transforming a serial scrambler to a parallel scrambler, a parallel scrambler and a double-edge-triggered register with XOR operation are provided. The method transforms a serial scrambler to a parallel scrambler according to a characteristic polynomial: P ⁡ ( x ) = ∑ q = 0 N ⁢ c q ⁢ x q ⁢ ⁢ or ⁢ ⁢ b ⁡ ( i ) = ∑ q = 1 N ⁢ c q ⁢ b ⁡ ( i - q ) . The method first determines a transformation formula: b ⁡ ( kN + i ) = ∑ q = 1 N ⁢ c q ⁢ b ⁡ ( ( k - R ) ⁢ N + i + R ⁡ ( N - q ) ) according to the parameters of the characteristic polynomial. The parallel bits Bj=[bMj, bMj+1, . . . , bMj+M-2, bMj+M-1] are arranged in order. The transformation number R=2t (the initial number of t is 0) is set. The parallel bits are replaced by the transformation formula. When (k-R)N+i+R(N-q) is larger than Mj-1 in the transformation formula, 1 is added to t in the transformation formula R=2t and the transformation formula is re-counted. Finally, the XOR gates are connected to the registers according to a computed result from the transformation formula.
申请公布号 US7639801(B2) 申请公布日期 2009.12.29
申请号 US20050096957 申请日期 2005.03.31
申请人 NATIONAL CENTRAL UNIVERSITY 发明人 JOU SHYH-JYE;CHEN CHIH-NING;WANG YOU-JIUN;HSIAO JU-YUAN;LIN CHIH-HSIEN
分类号 H04L9/00;H03M7/00;H04L9/18 主分类号 H04L9/00
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