发明名称 WAFER LEVEL PACKAGE AND MANUFACTURING METHOD THEREOF
摘要 <p>PURPOSE: A wafer level package and a manufacturing method thereof are provided to prevent a cracking due to a thermal expansion of mechanical impact to a substrate by forming a second bump on a buffer pattern on a first bump. CONSTITUTION: In a device, a plurality of chip pads(120) are formed on a substrate(110). The chip pad is exposed by the first passivation layer(130). A via(135) is connected to the chip pad through the first passivation layer. The metal wiring layer(140) is formed on the first passivation layer. An under bump metal(143) is connected to the metal wiring layer on the first passivation layer. A buffer pattern(145) separated through a trench(160) is formed at the bump metal. The second passivation layer(150) is formed on the first passivation layer. A first bump(170) is formed on the buffer pattern. A second bump(180) is formed on the first bump and the under bump metal.</p>
申请公布号 KR20090131045(A) 申请公布日期 2009.12.28
申请号 KR20080056817 申请日期 2008.06.17
申请人 SAMSUNG ELECTRO-MECHANICS CO., LTD. 发明人 JEON, HYUNG JIN;YI SUNG;LEE, JONG YUN;KWEON YOUNG DO;BAEK, JONG HWAN
分类号 H01L23/12;H01L21/60;H01L23/50 主分类号 H01L23/12
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