| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To overcome the tradeoff of a cost increase and the deterioration of performance which causes difficulty to the application of power gating. <P>SOLUTION: A semiconductor device has: a p-type substrate 2; and a first p-well 4 and a second p-well 5 which are formed away from each other in the p-type substrate 2. An n-type logic transistor LTn is formed at the first p-well 4, and a power supply interception transistor PGT is formed at the second p-well 5. A shielding part (for example, two PN junctions) which shields voltage potential interference in the p-type substrate 2 is formed between the first p-well 4 and the second p-well 5. A substrate contact region 11 for applying a substrate bias voltage VBB to power supply interception transistor PGT is formed in a substrate region on the second p-well 5 side of two substrate regions in which voltage potential interference is shielded by the shielding part. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
