发明名称 LAYOUT SYSTEM AND LAYOUT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To improve processing speed during correction of layout. Ž<P>SOLUTION: The layout system 1 includes: a layout creation means 2 to create the layout of circuit elements and wiring; a dummy pattern creation means 3 to create a dummy pattern for the layout which is created by the layout creation means 2; a layout correction means 3 to correct the layout which is created by the layout creation means 2; and a dummy pattern reuse means 4 to reuse the dummy pattern for the layout which is created by the layout creation means 2 and to create a dummy pattern for the layout which is corrected by the layout correction means 3. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2009302179(A) 申请公布日期 2009.12.24
申请号 JP20080152785 申请日期 2008.06.11
申请人 NEC ELECTRONICS CORP 发明人 SHIMOBEPPU MASAYUKI
分类号 H01L21/82;G06F17/50;H01L21/822;H01L27/04 主分类号 H01L21/82
代理机构 代理人
主权项
地址