发明名称 |
METHOD OF FABRICATING SEMICONDUCTOR DEVICE |
摘要 |
<P>PROBLEM TO BE SOLVED: To provide a method of fabricating a semiconductor device in which a plurality of silicide layers each having a low resistance value are formed adjacent to one another via insulating films and a deterioration in voltage endurance characteristics and the occurrence of short circuit among the plurality of silicide layers are suppressed. Ž<P>SOLUTION: The method of fabricating the semiconductor device according to one embodiment includes: forming a plurality of Si-based pattern portions above a semiconductor substrate, the plurality of Si-based pattern portions being adjacent in a direction substantially parallel to a surface of the semiconductor substrate via the insulating films; forming a metal film above the plurality of Si-based pattern portions and the insulating films so as to contact with the plurality of Si-based pattern portions; processing whole areas or upper portions of the plurality of Si-based pattern portions into the plurality of silicide layers by a silicidation reaction between the plurality of Si-based pattern portions and the metal film by heat treatment; and removing the plurality of silicide layers formed above the insulating films by applying planarizing treatment to the plurality of silicide layers. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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申请公布号 |
JP2009302502(A) |
申请公布日期 |
2009.12.24 |
申请号 |
JP20080294773 |
申请日期 |
2008.11.18 |
申请人 |
TOSHIBA CORP |
发明人 |
HIRASAWA SHINICHI;WATANABE SHINYA |
分类号 |
H01L21/3205;H01L21/28;H01L21/8247;H01L23/52;H01L27/115;H01L29/423;H01L29/49;H01L29/788;H01L29/792 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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