发明名称 INFORMATION PROCESSOR
摘要 <P>PROBLEM TO BE SOLVED: To maximize the using efficiency of three kinds of buses which are a system bus, a memory bus and a processor bus. Ž<P>SOLUTION: The processor bus 111, the memory bus 112 and the system bus 113 to which an input/output device 105 is connected are connected to a three-forked road connection control means 103. The three-forked road connection control means includes a bus memory connection controller to which the address bus and control bus of the processor bus, the memory bus and the system bus are respectively connected, and which transfers addresses and control signals with each other and generates data bus control signals. Also, the three-forked road connection control means 103 includes a data path switch to which the data buses of the processor bus 111, the memory bus 112 and the system bus 113 respectively are connected and which mutually transfers data on the data buses according to the data bus control signals. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2009301568(A) 申请公布日期 2009.12.24
申请号 JP20090186221 申请日期 2009.08.11
申请人 HITACHI LTD 发明人 OKAZAWA KOICHI;MOCHIDA TETSUYA;KIMURA KOICHI;KAWAGUCHI HITOSHI;YUNO KAZUHARU;KOBAYASHI ICHIJI
分类号 G06F13/28;G06F13/16;G06F13/36 主分类号 G06F13/28
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