发明名称 Multi-chip stack package and fabricating method thereof
摘要 A multi-chip stack package includes a substrate, a first chip, a second chip, a plurality of bumps, a plurality of junction interface bumps, a plurality of conductive wires, a filler material and an encapsulating material. The substrate has a plurality of first contacts and a plurality of second contacts thereon. The first chip is bonded to the substrate surface by the bumps positioned between the active surface of the first chip and the first contacts. The second chip is bonded to the first chip by the junction interface bumps positioned between the back surface of the first chip and the back surface of the second chip. The conductive wires electrically connect the active surface of the second chip and the second contacts. The filler material encloses the bumps and the junction interface bumps. The encapsulating material encloses the first chip, the second chip and the conductive wires.
申请公布号 US7635610(B2) 申请公布日期 2009.12.22
申请号 US20070689507 申请日期 2007.03.21
申请人 ADAVNACED SEMICONDUCTOR ENGINEERING INC. 发明人 FANG JEN-KUANG
分类号 H01L21/00;H01L25/065 主分类号 H01L21/00
代理机构 代理人
主权项
地址