| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To improve decrease of a write margin under a low power supply voltage in a semiconductor storage device without lowering a write access time. <P>SOLUTION: At the time when data are written in, a bit line potential on a low side of bit line couple (BLi, /BLi) is detected, and when the bit line potential at the row side is lowered to a predetermined potential level, a negative voltage is generated by a negative voltage generating circuit (NVG) and this generated negative voltage is transmitted to the low side bit line through transfer gates (30a, 30b). <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
