| 摘要 |
PURPOSE:To check various device timings with a small amount of hardware by generating optional check signals at prescribed intervals during a system cycle and selecting them to check device timings. CONSTITUTION:Control signals 9-12 are selected by a selector 3 in accordance with output signals 19 and 20 of a mode register 5, and the selector 3 selects the signal 9 if mode signals 19 and 20 are '0' together, and the selector 3 selects the signal 10 if signals 19 and 20 are '0' and '1' respectively, and the selector 3 selects the signal 11 if signals 19 and 20 are '1' and '0' respectively, and the selector 3 selects the signal 12 if signals 19 and 20 are '1' together. Timing signals 13-16 are selected by a selector 4 in accordance with output signals 21 and 22 of the mode register 5, and the selector 4 selects the signal 13 if mode signals 21 and 22 are '0' together, and the selector 4 selects the signal 14 if signals 21 and 22 are '0' and '1' respectively, and the selector 4 selects the signal 14 if signals 21 and 22 are '1' and '0' respectively, and the selector selects the signal 16 if signals 21 and 22 are '1' together. AND between an output signal 17 of the selector 3 and an output signal 18 of the selector 4 is operated by an AND circuit 6 to obtain a check signal 23. |
