| 摘要 |
<P>PROBLEM TO BE SOLVED: To solve a problem that a 2-bit error containing a 1-bit error resulting from poor fastening of a bit line cannot be solved by a conventional error correction method. <P>SOLUTION: A semiconductor memory device comprises: a storage portion 10 having a reference data storage region, where a plurality of data storage cells storing a group of data in the direction of the same word line are arranged and reference data with predetermined values as data are stored, and a user data region where first user data entered from other circuits as data are stored; a writing control portion 20 that outputs poor bit line information A3 indicating the position of a bit line where poor fastening has occurred based on the reference data and the first user data; and an error correction circuit 70 that performs error correction for the first user data based on parity data for 1-bit correction contained in the poor bit line information A3 and the first user data. <P>COPYRIGHT: (C)2010,JPO&INPIT |
