发明名称 Performing Die-to-Wafer Stacking by Filling Gaps Between Dies
摘要 An integrated circuit structure includes a bottom semiconductor chip; a top die bonded onto the bottom semiconductor chip; a protecting material encircling the bottom die and on the bottom semiconductor chip; and a planar dielectric layer over the top die and the protecting material. The protecting material has a top surface leveled with a top surface of the top die.
申请公布号 US2009311829(A1) 申请公布日期 2009.12.17
申请号 US20080140695 申请日期 2008.06.17
申请人 发明人 YANG KU-FENG;CHIOU WEN-CHIH;WU WENG-JIN;SUNG MING-CHUNG
分类号 H01L21/48;H01L21/44 主分类号 H01L21/48
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