| 摘要 |
An integrated circuit die comprises a plurality of interconnects including a first test data input (142), a second test data input (144) and a test data output (152), and a test arrangement (100) for testing the integrated circuit die. The test arrangement (100) comprises a further multiplexer (150) coupled to the test data output (152), a multiplexer (140) coupled to the first test data input (142) and the second test data input (144), a plurality of shift registers (102, 104, 106, 108) including an instruction register (108), each of the shift registers being coupled between the multiplexer (140) and the further multiplexer (150) and a controller (110) for controlling the multiplexer (140) and the further multiplexer (150) in response to the instruction register (108). Such a test arrangement facilitates JTAG compliant testing of a system in package (SiP) by providing a direct connection between the SiP test data input pin and the second test data input (144) of the IC die, and the SiP test data output pin and the test data output (152) of the IC die, thus facilitating the bypassing of other test arrangements in the SiP.
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