发明名称
摘要 A method for manufacturing a flash memory device is provided to reduce a spacer margin by performing an ion injection process after removing an oxide layer of a gate device. A plurality of gate devices are formed on an active region of a semiconductor substrate(S401). An oxide-nitride-oxide layer is deposited in the front of the semiconductor substrate(S402). The oxide-nitride-oxide layer is removed on the substrate between devices by a dry etching method(S403). An NMOS implant and a PMOS implant are successively processed(S404). An oxide layer of the uppermost surface is removed(S405). The nitrogen is injected to supplement the nitrogen in the protective layer with an annealing(S406). The oxide-nitride-oxide layer is HTO-SiN-TEOS.
申请公布号 KR100932135(B1) 申请公布日期 2009.12.16
申请号 KR20070138386 申请日期 2007.12.27
申请人 发明人
分类号 H01L27/115;H01L21/8247;H01L29/78 主分类号 H01L27/115
代理机构 代理人
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