| 摘要 |
The device has a synchronization circuit (55) with a standard output that is connected to a control input of a multiplexer. The synchronization circuit includes a clock pulse output that is connected with a clock input (CLK) of a register. The synchronization circuit generates and outputs a clock pulse at the clock pulse output, where the clock pulse is derived from a time dependent signal at a status input and a signal at a clock input (4). An independent claim is also included for a method for synchronization of a data word. |
