发明名称 Multilayer electrical interconnect fabrication with few process steps
摘要 Method for making a multilayer electrical interconnect with stacked pillars between layers using a minimal number of conventional process steps. The method includes sputtering a chromium/copper/titanium trilayer on a dielectric base, depositing a patterned mask on the trilayer, etching the exposed trilayer, removing the mask, depositing a layer of polyimide over the unetched copper, forming a via in the polyimide above the copper, electrolessly plating nickel into the via, and polishing the interconnect to form a planar top surface.
申请公布号 US5118385(A) 申请公布日期 1992.06.02
申请号 US19910705843 申请日期 1991.05.28
申请人 MICROELECTRONICS AND COMPUTER TECHNOLOGY CORPORATION 发明人 KUMAR, NALIN;LIN, CHARLES W. C.
分类号 H01L21/48;H01L23/498;H05K3/42;H05K3/46 主分类号 H01L21/48
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