| 摘要 |
PURPOSE:To attain the parallel processing together with a CPU, by decoding an instruction code transmitted from the CPU, designating the address of a memory device sequentially, and eliminating increment of the number of connecting lines with the CPU even if the storage capacity is increased. CONSTITUTION:An instruction code among data D1-D4 transmitted from the CPU is decoded at a decoder 6b, transmitted to a timing generating circuit 6a, and control instructions O1-O7 are outputted. An address of an RAM20 is designated accoding to the control instructions O1-O7. Thus, even if the capacity of the RAM20 is increased, the number of bus lines connected to the CPU is not increased. Further, the movement of data in the RAM20 and the search of data are processed automatically independently of the CPU. Then, the CPU performs other processings in parallel. |
