CLOCK DATA RECOVERY CIRCUIT, METHOD AND TEST DEVICE UTILIZING THEM

摘要

A change point detection circuit (16) extracts a clock signal (S3) from an input data, i.e. a serial data (S1). A variable delay circuit (40) imparts a delay dependent on a delay control signal (S8a) to a reference signal (S4) having a predetermined frequency, and shifts the phase of the reference signal (S4) with reference to an initial delay. An input latch circuit (14) latches internal serial data (S2) using the output signal from the variable delay circuit (40) as a strobe signal (S5). A phase comparator (22) matches the frequencies of the clock signal (S3) and the strobe signal (S5) and generates phase difference data (S9) dependent on the phase difference of two signals. A loop filter (30) integrates the phase difference data (S9) generated by the comparator (22) and outputs the delay control signal (S8a). A phase shift amount acquisition section (50) acquires the amount of phase shift with reference to the initial delay imparted to the reference signal by the variable delay circuit (40) based on the delay control signal (S8a).