| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To reduce jitters generated in a reproduced clock signal CK, since the deviation of the output cycle in enable period can be removed, even when a plurality of specific data are inserted in a generation period of a single cycle in the enable period. <P>SOLUTION: When generating a clock reproducing signal ED formed by alternately generating the enable period EN in the ratio (N/M) of client data for the clock number of N to line data for the clock number of M and disable periods D1-D4 as shown in (a), taking pulse-stuffing detection in the line data as a chance as expressed by the code m0 in (b), the clock-reproducing signal ED is generated, by advancing the phase of the disable period D2 by a phase equivalent to the disable period (a period for the clock number of 1) during the enable period, with reference to phase information added to the clock-reproducing signal, as shown in (c). <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
