发明名称 Multiprocessor type time varying image encoding system and image processor with memory bus control table for arbitration priority
摘要 A multiprocessor type time varying image encoding system having a plurality of digital signal processor (DSP) modules (DMM's) connected in parallel, each DMM having a DSP, a local memory and an interrupt control unit, a plurality of common memories for storing data which is being processed, parameters, etc., an input frame memory which enables reading and writing operations to be executed asynchronously, a combination of a task control unit and a task table for distributing tasks to the DMM's, a plurality of independent common buses, and a combination of a bus control unit and a bus control table for bus sharing control.
申请公布号 US5237686(A) 申请公布日期 1993.08.17
申请号 US19920944404 申请日期 1992.09.14
申请人 MITSUBISHI DENKI KABUSHIKI KAISHA 发明人 ASANO, KENICHI;SUZUKI, RYUTA
分类号 G06T1/20;G06T9/00;H04N7/26 主分类号 G06T1/20
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