发明名称 DEAD TIME CONTROL CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a circuit for reducing switching loss in a synchronous rectifying circuit of a switching stage including a high-side control transistor and a low-side synchronous rectifying transistor which is coupled at a switching node. Ž<P>SOLUTION: A switching stage receives an input voltage and provides a controlled output voltage at an output contact. A circuit includes a first circuit portion and a second circuit portion. The first circuit portion senses the waveshape edges of a first signal at a gate terminal of the low-side synchronous rectifying transistor and a first voltage to determine a delay between the waveshape edge of the first signal and the waveshape edge of the first voltage. The second circuit portion calibrates the first signal and the first voltage to align the waveshape edge of the first signal and the waveshape edge of the first voltage, with an optional offset to attain minimal power loss. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2009290812(A) 申请公布日期 2009.12.10
申请号 JP20080144027 申请日期 2008.06.02
申请人 INTERNATL RECTIFIER CORP 发明人 KIM SEUNGBEOM KEVIN;VACCA TODD;JASON ZHANG
分类号 H03K17/16;H02M3/155;H03K17/687 主分类号 H03K17/16
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