| 摘要 |
<P>PROBLEM TO BE SOLVED: To shorten latency until a core acquires data in cache mistake without increasing the circuit scale. <P>SOLUTION: An MIDQ 104 is arranged at the input section of a data memory 106, and when move-in is executed, data to be transferred from an MAC 115 to the data memory 106 are temporarily stored. Also, after the data are written in the data memory 106, the MIDQ 104 outputs the same data through a line L0 to a selector 107. The line L0 is arranged only in the periphery of the data memory 106 so that the input section and output section of the data memory 106 are connected to each other. The selector 107 is arranged at the output section of the data memory 106, and either the data through the line L0 or the data output from the data memory 106 are selected. When move-in is executed, the selector 107 transfers the data through the line L0 to the core 101. <P>COPYRIGHT: (C)2010,JPO&INPIT |
