发明名称 |
SCHEME TO ALLEVIATE SIGNAL DEGRADATION CAUSED BY DIGITAL GAIN CONTROL LOOPS |
摘要 |
An amplifier (10) comprises a digitally clocked automatic gain control loop (11, 12, 13, 14). A Pseudo random clock generator (14) generates the clock signals for the loop. The application introduces a scheme which reduces sidebands caused by digital gain control loops. The effect of gain control on a system can be seen as amplitude modulation on the signal whose amplitude is controlled. This amplitude modulation causes the same sidebands that are commonly seen with AM modulation. This invention introduces a novel method that alleviates AM sidebands for a digitally controlled gain control loop.
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申请公布号 |
US2009304112(A1) |
申请公布日期 |
2009.12.10 |
申请号 |
US20070282572 |
申请日期 |
2007.03.12 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
LOMAS DAVID;AHLES STEPHAN |
分类号 |
H04L27/22;H03G3/00;H04L27/08 |
主分类号 |
H04L27/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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