| 摘要 |
Carbon nanotube memory comprises a buffered data path including a forwarding write line and a returning read line for transferring data. Furthermore, bit line is multi-divided for reducing parasitic capacitance, so that multi-stage sense amps are used for reading, wherein a local sense amp receives a memory cell output through the bit line, a segment sense amp receives a local sense amp output, and a global sense amp receives a segment sense amp output. By the sense amps, a voltage difference in the bit line is converted to a time difference for differentiating high data and low data. For example, high data is quickly transferred to an output latch circuit through the sense amps with high gain, but low data is rejected by a locking signal based on high data as reference signal. Additionally, alternative circuits and memory cell structures for implementing the memory are described.
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