发明名称 Word Line to Bit Line Spacing Method and Apparatus
摘要 In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line.
申请公布号 US2009302380(A1) 申请公布日期 2009.12.10
申请号 US20080134740 申请日期 2008.06.06
申请人 QIMONDA AG 发明人 GRAF WERNER;HEINECK LARS;POPP MARTIN
分类号 H01L27/105;H01L21/762 主分类号 H01L27/105
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