发明名称 CIRCUIT OPERATION VERIFICATION METHOD AND APPARATUS
摘要 <P>PROBLEM TO BE SOLVED: To verify an operation of a circuit change added for reduction of power consumption while reducing the operation load of a designer. <P>SOLUTION: In order to confirm a propagation range of a signal whose signal value is fixed by a control signal to restrain operations is within a predetermined range, it is determined by results of the logic simulation whether an operation restraining mode is enabled. If it is enabled, an operation probability restraint information list including the detected time and an ID of the net whose signal value is fixed is set to the net whose signal value is fixed, and then is propagated to the next net according to the results of the logic simulation. If the circuit changes are appropriated conducted, the results of the logic simulation do not satisfy the propagation condition of the operation probability restraint information list. Accordingly, the operation probability restraint information list is not propagated over the predetermined range, and no problem is detected. <P>COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2009289072(A) 申请公布日期 2009.12.10
申请号 JP20080141572 申请日期 2008.05.29
申请人 FUJITSU LTD 发明人 KANAZAWA YUJI
分类号 G06F17/50;G01R31/28;G06F11/22 主分类号 G06F17/50
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