| 摘要 |
<P>PROBLEM TO BE SOLVED: To generate an enable signal matching the rate of client data to line data at high speed. <P>SOLUTION: In the output period of a clock signal CK of M clocks (M: a positive integer), an enable signal EN1 having a period of N clocks (N: a positive integer, and N<M) is generated. An adding circuit 11 performs addition processing by one each time one clock of the CK is supplied, adds a first addition value obtained from a first formula (M-N) to an addition result AD1 when the AD1 is a negative value or adds a second addition value obtained from a second formula äM×(P-Q)÷P-N} (where P is an integer of ≥2, Q is an integer of ≥0, and Q<P<M) to the AD1 when the AD1 is 0 or a positive value, and outputs the AD1 after the addition. A frequency dividing counter 12 performs P frequency division of the CK only in a period wherein the AD1 is the positive value, and outputs a count value CK1. A comparator 13 outputs EN1 in a period wherein the AD1 is the negative value or when the CK1 is not less than Q. <P>COPYRIGHT: (C)2010,JPO&INPIT |
