发明名称 TEST APPARATUS, TEST METHOD, AND INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide testing device, test method and integrated circuit for testing a circuit having a counter, in a short time. SOLUTION: In the device, an up counter 12 and an down counter 13 are provided on a BIST circuit 1. The outputs of the up counter 12 and the down counter 13 are input into selector 2, sequentially being output in testing of memory 8. When LSI 10 itself is to be tested, the up counter 12 and the down counter 13 are operated in parallel. The selector 2 selects and outputs the up counter 12. Output of the down counter 13 is input into inverting circuit 3. In comparison circuit 4, up counter output from the selector 2 is compared with inversion signal of down counter output from the inverting circuit 3. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2009288199(A) 申请公布日期 2009.12.10
申请号 JP20080143771 申请日期 2008.05.30
申请人 FUJITSU LTD 发明人 DEGUCHI CHIKAHIRO;SEKINO YUTAKA;SHIBAZAKI SHOGO;GAMA SHINKICHI;NAGASE TAKESHI;NEGI HIDEYUKI
分类号 G01R31/28;H01L21/822;H01L27/04 主分类号 G01R31/28
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