| 摘要 |
An integrated circuit aims to decrease a parasitic resistance between an input protection circuit cell and a power supply cell including a clamp circuit, restrain a size of a diode from increasing beyond ESD robustness of the diode itself in order to compensate for a decrease in the ESD robustness, and prevent high-frequency signal power from decreasing due to a large capacitance component from a diode in an input protection circuit and a parasitic resistance component from a series resistor. The input protection circuit cell includes: an input terminal coupled to a signal pin; an output terminal coupled to not only a high-frequency circuit but also the input terminal and a node; a diode that is provided between the node and VDD and makes an electric current flow from the node to VDD; another diode that is provided between the node and GND and makes an electric current flow from GND to the node; and a clamp circuit coupled between VDD and GND parallel to the diodes.
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