METHODS AND APPARATUS FOR POWER REDUCTION IN A TRANSCEIVER
摘要
An integrated circuit for achieving power reduction in a transceiver may include a jammer detector that determines an interference level corresponding to a received signal, and a transmit power detector that determines a required transmit power level for a transmitted signal. The integrated circuit may also include at least one of the following: a process monitor that determines process corners of components within the receiver and/or the transmitter, and a temperature monitor that determines a temperature of the receiver and/or the transmitter. The integrated circuit may also include a state machine. The state machine may transition the receiver from a high linearity mode to a low linearity mode if a set of operating conditions is satisfied. Similarly, the state machine may transition the transmitter from a high power mode to a low power mode if a set of operating conditions is satisfied.
申请公布号
WO2009149082(A2)
申请公布日期
2009.12.10
申请号
WO2009US45971
申请日期
2009.06.02
申请人
QUALCOMM INCORPORATED;GUDEM, PRASAD, S.;CICCARELLI, STEVEN, C.;MOK, KEN TSZ KIN;KWOK, SAI, C.
发明人
GUDEM, PRASAD, S.;CICCARELLI, STEVEN, C.;MOK, KEN TSZ KIN;KWOK, SAI, C.