发明名称 |
Data inversion register technique for integrated circuit memory testing |
摘要 |
A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are "worst case" for I/O circuitry or column stripes which are "worst case" for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.
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申请公布号 |
US7631233(B2) |
申请公布日期 |
2009.12.08 |
申请号 |
US20070868509 |
申请日期 |
2007.10.07 |
申请人 |
UNITED MEMORIES, INC.;SONY CORPORATION |
发明人 |
PARRIS MICHAEL C.;JONES, JR. OSCAR FREDERICK |
分类号 |
G11C29/00;H04L1/00 |
主分类号 |
G11C29/00 |
代理机构 |
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