| 摘要 |
PURPOSE: A semiconductor memory device is provided to synchronize a phase of a data clock and a system clock very quickly by performing an auto clock alignment training mode. CONSTITUTION: A clock input unit(300) is inputted with a system clock and a data clock. A clock demultiply unit(320) generates a data demultiply clock by demultiplying a frequency of the data clock. The clock demultiply unit determines a phase of the data demultiply clock according to a demultiply control signal. A phase dividing unit(330) generates plural multi phase data demultiply clocks each having a phase difference of an expected size in response to the data demultiply clock. A first phase detection unit(340) detects a phase of the system clock based on a phase of an expected selection clock among the plural multi phase data demultiply clocks. The first phase detection unit generates the demultiply control signal according to the detection result.
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