| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a sample hold circuit capable of lowering a consumption power required for charging a capacitor without reducing a time allocated to a sample/hold for an input signal. Ž<P>SOLUTION: The sample hold circuit has a first capacitor pair 111A and 112A successively repeating a first operating mode receiving a positive-phase input signal and a negative-phase input signal respectively and charging charges, a second operating mode short-circuiting a section between an inverting input terminal and a non-inverting output terminal for an operational amplifier 130 and the section between a non-inverting input terminal and an inverting output terminal respectively while holding charges charged in the first operating mode and outputting a positive-phase output signal and a negative-phase output signal and a third operating mode discharging holding charges. The sample hold circuit further has a second capacitor pair 111B and 112B transferred to the third operating mode when the operating modes of the first capacitor pair are the first and second operating modes and the first and second operating modes when the operating modes of the first capacitor pair are the third operating mode respectively. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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