发明名称 |
Selective Per-Cycle Masking Of Scan Chains For System Level Test |
摘要 |
Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.
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申请公布号 |
US2009300446(A1) |
申请公布日期 |
2009.12.03 |
申请号 |
US20080341996 |
申请日期 |
2008.12.22 |
申请人 |
RAJSKI JANUSZ;CZYSZ DARJUSZ;MRUGALSKI GRZEGORZ;MUKHERJEE NILANJAN;TYSZER JERZY |
发明人 |
RAJSKI JANUSZ;CZYSZ DARJUSZ;MRUGALSKI GRZEGORZ;MUKHERJEE NILANJAN;TYSZER JERZY |
分类号 |
G01R31/3177;G06F11/25 |
主分类号 |
G01R31/3177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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