| 摘要 |
A voltage boost circuit is driven with a clock signal CLK which toggles between voltages V1 and V2. A first MOSFET is coupled between CLK and an output node OUT, and at least one additional MOSFET is coupled between OUT and a supply voltage. The first terminal of a capacitance is coupled at its first terminal to OUT, and at its second terminal to a delay circuit arranged to toggle its output to ~V2 or ~V1 a predetermined amount of time after the voltage applied to the clock signal side of the first MOSFET toggles to ~V2 or ~V1, respectively. The capacitance is charged to ~V2 when the voltage applied to the clock signal side of the first MOSFET toggles to ~V2, and OUT is increased to a voltage greater than V2 when the output of the delay circuit toggles to ~V2. The only active device junctions subjected to the boosted voltage are MOSFET well-substrate junctions, such that no active devices are overstressed.
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