CLOCK REPRODUCTION SIGNAL GENERATION METHOD AND CLOCK REPRODUCTION CIRCUIT

摘要

It is possible to eliminate a deflection of an output cycle of an enable period even when a plurality of specific data are inserted into one-cycle generation period of the enable period. Thus, it is possible to reduce a jitter generated in a reproduction clock signal CK. As shown in (a), a clock reproduction signal (ED) is generated by alternately generating an enable period (EN) of a ratio (N/M) of N-clock client data against M-clock line data and disable periods (D1 to D4). Upon detection of a stuffing pulse in line data as shown by a symbol m0 in (b) when generating the clock reproduction signal (ED), phase information attached to the clock reproduction signal (ED) is referenced so as to advance the phase of the disable period (D2) by a phase equivalent to a disable period between enable periods (such as one-clock period) as shown in (c).