发明名称 METHOD TO REDUCE VARIATION IN CMOS DELAY
摘要 Controlled voltage circuit for compensating the performance variations in integrate circuits caused by voltage supply, temperature, and process variations is proposed. The controlled voltage circuit includes several MOSFET transistors connected in series, a unity gain operational amplifier, and a constant current source with an input terminal and an output terminal. The input source terminal of the first MOSFET is connected to a constant current source and to the unity gain operational amplifier. The output terminal of the circuit is connected to the CMOS delay block. To compensate for the performance variation, the output voltage node at or before the unity gain operational amplifier is shifted higher as the operating process state is slowed down or as the temperature is increased. Conversely, the output voltage node is shifted lower as the process becomes faster or the temperature is reduced.
申请公布号 US2009295466(A1) 申请公布日期 2009.12.03
申请号 US20080129683 申请日期 2008.05.30
申请人 TRUONG PHAT;NGUYEN JON 发明人 TRUONG PHAT;NGUYEN JON
分类号 G05F1/10 主分类号 G05F1/10
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