| 摘要 |
A scan flip-flop device has a scan flip-flop, a Nch insulated gate field effect transistor and a Pch insulated gate field effect transistor. The Nch insulated gate field effect transistor is located on an output side the scan flip-flop. The Nch insulated gate field effect transistor turns off and dose not output a signal when a test enable signal is in a disable mode. The Pch insulated gate field effect transistor is located between a higher voltage source and an output side of the Nch insulated gate field effect transistor. The Pch insulated gate field effect transistor turns on when a test enable signal is in a disable mode. The Pch insulated gate field effect transistor sets a SO port at a high level voltage.
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