发明名称 |
DATA CONTROLLING IN THE MBIST CHAIN ARCHITECTURE |
摘要 |
A memory collar including a first circuit and a second circuit. The first circuit may be configured to generate one or more data sequences in response to one or more test commands. The one or more data sequences may be presented to a memory during a test mode. The second circuit may be configured to pre-process one or more outputs generated by the memory in response to the one or more data sequences.
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申请公布号 |
US2009300440(A1) |
申请公布日期 |
2009.12.03 |
申请号 |
US20080167305 |
申请日期 |
2008.07.03 |
申请人 |
ANDREEV ALEXANDRE;BOLOTOV ANATOLI;GRINCHUK MIKHAIL |
发明人 |
ANDREEV ALEXANDRE;BOLOTOV ANATOLI;GRINCHUK MIKHAIL |
分类号 |
G11C29/04;G06F11/27 |
主分类号 |
G11C29/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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