发明名称 DESIGN METHOD FOR SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE LAYOUT DESIGN DEVICE
摘要 <p><P>PROBLEM TO BE SOLVED: To provide the design method of a semiconductor package and a semiconductor package layout design device for stabilizing a power source noise characteristics, and for reducing operation man-hours. <P>SOLUTION: This design method includes: determining a wire wiring diagram of a semiconductor package similar with a new semiconductor package among the wire wiring diagrams of an existing semiconductor package designed in the past prior to the design of a new semiconductor package; determining a ball layout whose ball arrangement makes excellent power source noise characteristics from among the ball layout of the existing semiconductor package for the determined wire wiring diagram; and calculating inductance and resistance from a pad to which a power source has been assigned to a ball terminal for a power source based on the determined wire wiring diagram and ball layout to predict power source noise characteristics. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2009283779(A) 申请公布日期 2009.12.03
申请号 JP20080135810 申请日期 2008.05.23
申请人 FUJITSU MICROELECTRONICS LTD 发明人 MATSUZAWA TAKAYUKI
分类号 H01L23/12 主分类号 H01L23/12
代理机构 代理人
主权项
地址