| 摘要 |
An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a clock divider generating first and second intermediate signals having edges delayed from first edges of a clock signal having a first frequency. Each of the first and second intermediate signals has a second frequency that is half of the first frequency. The first and second intermediate signals have a phase difference of 180° from each other. The apparatus also includes a first delay element delaying the first intermediate signal by a first delay amount; a second delay element delaying the first intermediate signal by a second delay amount; a third delay element delaying the second intermediate signal by a third delay amount; and a fourth delay element delaying the second intermediate signal by a fourth delay amount. The third delay amount is equal to the first delay amount. The fourth delay amount is equal to the second delay amount. The apparatus also includes a delay detection loop to adjust the second and fourth delays.
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