发明名称 VIRTUAL MACHINE SYSTEM
摘要 PROBLEM TO BE SOLVED: To provide an LPAR environment capable of performing the I/O access of a 32 bit address mode in a server having a general-purpose IO bus represented by a PCI-Express bus. SOLUTION: (1) When an IO transaction issued by an OS on an LPAR is a 32 bit format, and a converted absolute address exceeds a 32 bit space, the packet format of an IO transaction is converted. (2) When an ECRC is applied to the IO transaction issued by the OS on the LPAR, the ECRC is recalculated so as to be normally received by the final reception destination. (3) When the ECRC is already an error, an ECRC pattern with which the same error is reproduced is generated, and applied to a packet. (4) Concerning ECRC generation, a 32 bit CRC arithmetic unit and a 64 bit CRC arithmetic unit are loaded, and the ECRCs are simultaneously calculated, and a correct CRC arithmetic result is selected based on data length on the bus in generating a packet. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2009282651(A) 申请公布日期 2009.12.03
申请号 JP20080132627 申请日期 2008.05.21
申请人 HITACHI LTD;HITACHI INFORMATION & COMMUNICATION ENGINEERING LTD 发明人 TAMURA TAKATSUGU;UENO HITOSHI;KOIKE HARUJI
分类号 G06F12/02;G06F9/46;G06F11/10 主分类号 G06F12/02
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